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4k x 8/9 dual-port static ram fax id: 5204 cy7c138 cy7c139 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 november 1996 1cy 7 c13 9 features ? true dual-ported memory cells which allow simultaneous reads of the same memory location ? 4k x 8 organization ( cy7c138) ? 4k x 9 organization ( cy7c139) ? 0.65-micron cmos for optimum speed/power ? high-speed access: 15 ns ? low operating power: i cc = 160 ma (max.) ? fully asynchronous operation ? automatic power- down ? ttl compatible ? expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device ? on-chip arbitration logic ? semaphores included to permit software handshaking between ports ? int flag for port-to-port communication ? available in 68-pin plcc functional description the cy7c138 and cy7c139 are high-speed cmos 4k x 8 and 4k x 9 dual-port static rams. various arbitration schemes are included on the cy7c138/9 to handle situations when mul- tiple processors access the same piece of data. two ports are provided permitting independent, a synchronous access for reads and writes to any location in memory. the cy7c138/9 can be utilized as a standalone 8/9-bit dual-port static ram or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor designs, communications sta- tus buffering, and dual-port video/graphics memory. each port has independ ent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a chip enable (ce ) pin or sem pin. the cy7c138 and cy7c139 are available in a 68-pin plcc. notes: 1. busy is an output in master mode and an input in slave mode. 2. interrupt: push-pull output and requires no pull-up resistor. c138-1 r/w l ce l oe l a 11 l a 0l a 0r a 11 r r/w r ce r oe r i/o 7l i/o 0l i/o 7r i/o 0r interrupt semaphore arbitration control i/o control i/o memory array address decoder address decoder sem l sem r busy l busy r int l int r m/s (7c139) i/o 8l i/o 8r (7c139) logic block diagram [2] [2] [1, 2] [1, 2] r/w l ce l oe l r/w r ce r oe r
cy7c138 cy7c139 2 pin configurations \ notes: 3. i/o 8r on the cy7c139. 4. i/o 8l on the cy7c139. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 top view 68-pin plcc 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 3334353637383940414243 5432168 666564636261 a 4l a 3l a 2l a 1l a 0l int l busy l gnd m/s busy r int r a 0r i/o 2l i/o 3l i/o 4l i/o 5l gnd i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r v cc 2728 29 30 98 7 6 47 46 45 44 a 1r a 2r a 3r a 4r i/o 3r i/o 4r i/o 5r i/o 6r 25 26 a 5l c138-2 cy7c138/9 pin definitions left port right port description i/o 0lC7l(8l) i/o 0rC7r(8r) data bus input/output a 0lC11l a 0rC11r address lines ce l ce r chip enable oe l oe r output enable r/w l r/w r read/write enable sem l sem r semaphore enable. when asserted low, allows ac cess to eight sema- phores. the three least significant bits of the address lines will determine which semaphore to write or read. the i/o 0 pin is used when wri ting to a semaphore. semaphores are requested by writ ing a 0 into the respective location. int l int r interrupt flag. int l is set when right port writes location ffe and is cleared when left port reads location ffe. int r is set when left port writes location fff and is cleared when right port reads location fff. busy l busy r busy flag m/s master or slave select v cc power gnd ground selection guide 7c138-15 7c139-15 7c138-25 7c139-25 7c138-35 7c139-35 7c138-55 7c139-55 maximum ac cess time (ns) 15 25 35 55 maximum operating current (ma) commercial 220 180 160 160 maximum standby current for i sb1 (ma) commercial 60 40 30 30
cy7c138 cy7c139 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. C65 c to +150 c ambient temperature with power applied............................................. C55 c to +125 c supply voltage to ground potential ............... C0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... C0.5v to +7.0v dc input voltage [5] ......................................... C0.5v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... >2001v (per milCstdC883, method 3015) latchCup current ................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial C40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c138-15 7c139-15 7c138-25 7c139-25 unit min. max. min. max. v oh output high voltage v cc = min., i oh = C4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 v v ih 2.2 2.2 v v il input low voltage 0.8 0.8 v i ix input le akage current gnd < v i < v cc C10 +10 C10 +10 m a i oz output leakage current output disabled, gnd < v o < v cc C10 +10 C10 +10 m a i cc operating current v cc = max., i out = 0 ma, outputs disabled coml 220 180 ma ind 190 i sb1 standby current (both ports ttl levels) ce l and ce r > v ih , f = f max [6] coml 60 40 ma ind 50 i sb2 standby current (one port ttl level) ce l and ce r > v ih , f = f max [6] coml 130 110 ma ind 120 i sb3 standby current (both ports cmos levels) both ports ce and ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, f = 0 [6] coml 15 15 ma ind 30 i sb4 standby current (one port cmos level) one port ce l or ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, active port outputs, f = f max [6] coml 125 100 ma ind 115 notes: 5. pulse width < 20 ns. 6. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 .
cy7c138 cy7c139 4 ] electrical characteristics over the operating range (continued) parameter description test conditions 7c138-35 7c139-35 7c138-55 7c139-55 unit min. max. min. max. v oh output high voltage v cc = min., i oh = C4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 v v ih 2.2 2.2 v v il input low voltage 0.8 0.8 v i ix input le akage current gnd < v i < v cc C10 +10 C10 +10 m a i oz output leakage current output disabled, gnd < v o < v cc C10 +10 C10 +10 m a i cc operating current v cc = max., i out = 0 ma, outputs disabled coml 160 160 ma ind 180 180 i sb1 standby current (both ports ttl levels) ce l and ce r > v ih , f = f max [6] coml 30 30 ma ind 40 40 i sb2 standby current (one port ttl level) ce l and ce r > v ih , f = f max [6] coml 100 100 ma ind 11 0 110 i sb3 standby current (both ports cmos levels) both ports ce and ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, f = 0 [6] coml 15 15 ma ind 30 30 i sb4 standby current (one port cmos level) one port ce l or ce r > v cc C 0.2v, v in > v cc C 0.2v or v in < 0.2v, active port outputs, f = f max [6] coml 90 90 ma ind 100 100 capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 15 pf ac test loads and waveforms note: 7. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd 90% 90% 10% <3ns <3 ns 10% all input pulses (a) normal load (load 1) r1=893 w 5v output r2=347 w c= 30 pf r th =250 w v th =1.4v output c=30pf (b) th venin equivalent (load 1) (c) three-state delay (load 3) c= 30pf output load (load 2) c138-3 c138-4 c138-5 c138-6 c138-7 r1=893 w r2=347 w 5v output c= 5pf
cy7c138 cy7c139 5 switching characteristics over the operating range [8] parameter description 7c138-15 7c139-15 7c138-25 7c139-25 7c138-35 7c139-35 7c138-55 7c139-55 unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 15 25 35 55 ns t aa address to data valid 15 25 35 55 ns t oha output hold from address ch ange 3 3 3 3 ns t ace ce low to data valid 15 25 35 55 ns t doe oe low to data valid 10 15 20 25 ns t lzoe [9,10,11] oe low to low z 3 3 3 3 ns t hzoe [9,10,11] oe high to high z 10 15 20 25 ns t lzce [9,10,11] ce low to low z 3 3 3 3 ns t hzce [9,10,11] ce high to high z 10 15 20 25 ns t pu [11] ce low to power-up 0 0 0 0 ns t pd [11] ce high to power-down 15 25 35 55 ns write cycle t wc write cycle time 15 25 35 55 ns t sce ce low to write end 12 20 30 40 ns t aw address set-up to write end 12 20 30 40 ns t ha address hold from write end 2 2 2 2 ns t sa address set-up to write start 0 0 0 0 ns t pwe write pulse width 12 20 25 30 ns t sd data set-up to write end 10 15 15 20 ns t hd data hold from write end 0 0 0 0 ns t hzwe [10,11] r/w low to high z 10 15 20 25 ns t lzwe [10,11] r/w high to low z 3 3 3 3 ns t wdd [12] write pulse to data delay 30 50 60 70 ns t ddd [12] write data valid to read data valid 25 30 35 40 ns busy timing [13] t bla busy low from address match 15 20 20 45 ns t bha busy high from address mismatch 15 20 20 40 ns t blc busy low from ce low 15 20 20 40 ns t bhc busy high from ce high 15 20 20 35 ns t ps port set-up for priority 5 5 5 5 ns t wb r/w low after busy low 0 0 0 0 ns t wh r/w high after busy high 13 20 30 40 ns t bdd [14] busy high to data valid note 13 note 13 note 13 note 13 ns interrupt timing [13] t ins int set time 15 25 25 30 ns t inr int reset time 15 25 25 30 ns
cy7c138 cy7c139 6 semaphore timing t sop sem flag update pulse (oe or sem )10 10 15 20 ns t swrd sem flag write to read time 5 5 5 5 ns t sps sem flag contention window 5 5 5 5 ns switching characteristics over the operating range [8] (continued) parameter description 7c138-15 7c139-15 7c138-25 7c139-25 7c138-35 7c139-35 7c138-55 7c139-55 unit min. max. min. max. min. max. min. max. switching waveforms notes: 8. test conditions assume si gnal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 9. at any given temperature and voltage con dition for any g iven device, t hzce is less than t lzce and t hzoe is less than t lzoe . 10. test conditions used are load 3. 11. this parameter is guaranteed but not tested. 12. for information on part-to-part delay through ram cells from writing port to reading port, refer to read timing with port-to-port delay waveform. 13. test conditions used are load 2. 14. t bdd is a calculated parameter and is the greater of t wdd - t pwe (actual) or t ddd - t sd (actual). 15. r/w is high for read cycle. 16. device is continu ously selected ce = low and oe = low. this waveform cannot be used for semaphore reads. 17. address valid prior to or coincident with ce transition low. 18. ce l = l, sem = h when accessing ram. ce = h, sem = l when accessing semaphores. t rc t aa t oha data valid previous data valid data out address c138-8 read cycle no. 1 (either port address ac cess) [15, 16] t ace t lzoe t doe t hzoe t hzce data valid data out sem or ce oe t lzce t pu i cc i sb t pd c138-9 read cycle no. 2 (either port ce /oe access) [15, 17, 18]
cy7c138 cy7c139 7 notes: 19. busy = high for the writing port. 20. ce l = ce r = low. 21. the internal write time of the memory is defined by the overlap of ce or sem low and r/w low. both signals must be low to initiate a write, and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/w controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t pwe . 23. r/w must be high during all address transitions. switching waveforms (continued) valid t ddd t wdd match match r/w r data inr data outl c138-10 t wc address r t pwe valid t sd t hd address l read timing with port-to-port delay (m/s = l) [19, 20] c138-11 t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe t lzoe sem or ce r/w oe data out data in address write cycle no. 1: oe three-states data i/os (either port) [21, 22, 23]
cy7c138 cy7c139 8 notes: 24. data i/o pins enter high impedance when oe is held low during write. 25. ce = high for the duration of the above timing (both write and read cycle). switching waveforms (continued) t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance sem or ce r/w data out datain t lzwe data valid c138-12 address write cycle no. 2: r/w three-states data i/os (either port) [21, 23, 24] t sop t aa sem r/w oe i/o 0 c138-13 valid address valid address t hd data in val id data out val id t oha a 0 Ca 2 t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle semaphore read after write timing, either side [25]
cy7c138 cy7c139 9 notes: 26. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high 27. sema phores are reset (available to both ports) at cycle start. 28. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side w ill control the sem aphore. switching waveforms (continued) match c138-14 t sps a 0l Ca 2l match r/w l sem l a 0r Ca 2r r/w r sem r timing diagram of semaphore contention [26, 27, 28] val id t ddd t wdd match match r/w r data in r data outl c138-15 t wc address r t pwe val id t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of read with busy (m/s =high) [20] t pwe r/w busy t wb t wh c138-16 write timing with busy input (m/s =low)
cy7c138 cy7c139 10 note: 29. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: c138-17 address l,r busy r ce l ce r busy l ce r ce l address l,r c138-18 ce l valid first: busy timing diagram no. 1 (ce arbitration) [29] address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r c138-19 c138-20 busy timing diagram no. 2 (address arbitration) left address valid first: right address valid first: [29]
cy7c138 cy7c139 11 notes: 30. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 31. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write fff t wc t ha read fff t rc t inr write ffe t wc read ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins c138-21 c138-22 c138-23 c138-24 interrupt timing diagrams left side sets int r : right side clears int r : right side sets int l : left side clears int l : [30] [30] [31] [31] [31] [31]
cy7c138 cy7c139 12 architecture the cy7c138/9 consists of an array of 4k words of 8/9 bits each of dualCport ram cells, i/o and address lines, and con- trol signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simul- taneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for portCtoCport communication. two semaphore (sem ) control pins are used for al- locating shared resources. with the m/s pin, the cy7c138/9 can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the cy7c138/9 has an automatic power-down fea- ture controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is con- trolled by either the oe pin (see write cycle no. 1 waveform) or the r/w pin (see write cycle no. 2 waveform). data can be written to the device t hzoe after the oe is deasserted or t hzwe after the falling edge of r/w . required inputs for non-contention operations are summa- rized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; oth- erwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user of the cy7c138/9 wishes to access a sema- phore flag, then the sem pin must be asserted instead of the ce pin. interrupts the interrupt flag (int ) permits communications between ports.when the left port writes to location fff, the right ports interrupt flag (int r ) is set. this flag is cleared when the right port reads that same location. setting the left ports interrupt flag (int l ) is accom- plished when the right port writes to location ffe. this flag is cleared when the left port reads location ffe. the message at fff or ffe is user-defined. see ta bl e 2 for input requirements for int . int r and int l are push-pull outputs and do not require pull-up resistors to op- erate. busy l and busy r in master mode are push-pull outputs and do not require pull-up resistors to operate. busy the cy7c138/9 provides on-chip ar bitration to alleviate simul- taneous memory location access (contention). if both ports ce s are asserted and an address match occurs within t ps of each other the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the de vice to in terface to a master de vice with no external components .writing of slave devices must be delayed until after the busy input has settled. otherwise, the slave chip may begin a write cycle during a contention situa- tion.when presented as a high inp ut, the m/s pin allows the device to be used as a master and therefore the busy line is an output. busy can then be used to send the arbitration out- come to a slave. semaphore operation the cy7c138/9 provides eight semaphore latches, which are separ ate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore loca- tion. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the sema- phore. the s emaphore value will be a vailable t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right p ort has control and continues to poll the semaphore.when the right side has relinquished co ntrol of the s emaphore (by writing a one), the left side will succeed in gaining control of the a sema- phore.if the left side no longer requires the se maph ore, a one is written to cancel its request. semaphores are accessed by asser ting sem low. the sem pin functions as a chip enable for the semaphore latches (ce must remain high during sem low). a 0C2 represents the semaph ore address. oe and r/w are used in the same man- ner as a normal memory access.when writing or reading a semaph ore, the other a ddress pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an unused s emap hore, a one will ap- pear at the same semaphore address on the right port. that semaph ore can now only be modified by the side showing zero (the left port in this case). if the left port now relinq uishes control by writing a one to the se maph ore, the s emaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. ta bl e 3 shows sample semaphore operations. when reading a semaphore, all eight/nine data lines output the semaphore value. the read value is latched in an output reg- ister to prevent the semaphore from changing state during a write from the other port. if both ports attempt to acc ess the semaphore wi thin t sps of each other, the semaphore will defi- nitely be obtained by one side or the other, but there is no guar- antee which side will control the s emaphore. initialization of the semaphore is not automatic and must be reset during initialization program at power-up. all sema- phores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
cy7c138 cy7c139 13 table 1. non-contending read/write inputs outputs operation ce r/w oe sem i/o 0-7/8 h x x h high z power-down h h l l data out read data in semaphore x x h x high z i/o lines disabled h x l data in write to semaphore l h l h data out read l l x h data in write l x x l illegal condition table 2. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w ce oe a 0-11 int r/w ce oe a 0-11 int set left int x x x x l l l x ffe x reset left int x l l ffe h x x x x x set right int l l x fff x x x x x l reset right int x x x x x x l l fff h table 3. semaphore operation example function i/o 0-7/8 left i/o 0-7/8 right status no action 1 1 semaphore free left port writes semaphore 0 1 left port obtains semaphore right port writes 0 to semaphore 0 1 right side is denied ac cess left port writes 1 to semaphore 1 0 right port is granted access to semaphore left port writes 0 to semaphore 1 0 no change. left port is denied ac cess right port writes 1 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore address right port writes 0 to semaphore 1 0 right port obtains semaphore right port writes 1 to semaphore 1 1 no port accessing semaphore left port writes 0 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore
cy7c138 cy7c139 14 typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 C55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 supplyvoltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature (c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 v cc =5.0v v in =5.0v 0 i cc i cc 1.6 1.4 1.2 1.0 0.8 -55 125 normalized access time vs. ambient temperature ambient temperature (c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 supplyvoltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 0 80 output voltage (v) output sink current vs. output voltage v cc =5.0v t a =25_c 0.6 0.8 v cc =5.0v t a =25c 1.25 1.0 0.75 10 0.50 normalized i cc vs.cycle time cycle frequency (mhz) 1.00 0.25 0 1.0 2.0 3.0 5.0 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 0 15.0 0.0 supplyvoltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 0.50 28 0.2 0.6 1.2 i sb3 0.2 0.4 i sb3 25 1.1 v cc =4.5v t a =25c v cc =5.0v t a =25c v in =0.5v 5.0 v cc =5.0v t a =25c 40 160 200 5.0 40 66 0.75
cy7c138 cy7c139 ? cypress s emiconduc tor corporation, 1996. the information contained herein is subject to change without noti ce. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. 4k x9 dual-port sram document #: 38C00536 ordering information 4k x8 dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c138C15jc j81 68Clead plastic l eaded chip car rier commercial 25 cy7c138C25jc j81 68Clead plastic l eaded chip car rier commercial cy7c138C25ji j81 68Clead plastic l eaded chip car rier industrial 35 cy7c138C35jc j81 68Clead plastic l eaded chip car rier commercial cy7c138C35ji j81 68Clead plastic l eaded chip car rier industrial 55 cy7c138C55jc j81 68Clead plastic l eaded chip car rier commercial cy7c138C55ji j81 68Clead plastic l eaded chip car rier industrial speed (ns) ordering code package type package type operating range 15 cy7c139C15jc j81 68Clead plastic l eaded chip car rier commercial 25 cy7c139C25jc j81 68Clead plastic l eaded chip car rier commercial cy7c139C25ji j81 68Clead plastic l eaded chip car rier industrial 35 cy7c139C35jc j81 68Clead plastic l eaded chip car rier commercial cy7c139C35ji j81 68Clead plastic l eaded chip car rier industrial 55 cy7c139C55jc j81 68Clead plastic l eaded chip car rier commercial cy7c139C55ji j81 68Clead plastic l eaded chip car rier industrial package diagram 68-lead plastic leaded chip carrier j81

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